导　　师： 邹雪城

学科专业： 080903

授予学位： 硕士

作　　者： ;

机构地区： 华中科技大学

摘　　要： 在已有模数转换器的基本结构中,逐次逼近/(Successive Approximation/)型和过采样/(Oversampling/)型可以实现比较高的精度,但受结构的限制这两种类型都难以实现更高的速度。流水线结构模数转换器是一种研究和应用非常广泛的模数转换器结构,在精度、速度和功耗上相对其它类型有很大的改进,是高速高精度领域的主要应用类型。 在高端可视信号处理,高速大规模数字通信,以及医疗呈像等领域的研究开发中,需要采样频率达到100MS//s,奈氏带宽的动态范围接60dB的ADC。为达到这些要求,人们对一种功能强大的,同时具有合理的面积和功耗的ADC的电路和结构进行了持续不断的研究。这里,我们对在标准CMOS工艺下实现这样一个ADC尤为关注。 本文首先讨论了在时间插入,或是并行,流水线结构ADC中的一些已知问题。然后,针对这些问题,我们给出一个10位的,最大采样频率95MHz的0.6um CMOS工艺下的结构,并进行说明。在低的转换速率下,它的信噪失真比/(Signal-to-Noise And Distortion–Ration/)达到59.5dB,而在50MHz输入频率,95MHz转换频率下,其SNDR可达到50dB。通过一个很小的失调控制来抑制fs//2处频谱,其无杂散动态范围/(SFDR/)可达到65dB。ADC由全差动电路实现,采用2通道3级流水线结构。每级转换4位,12位中的2位用于数字纠错。同时针对这种结构的次级模数转换器/(sub-ADC/)中的比较器结构,我们进行了深入的探讨和研究,并提出了一种优化的比较器结构,使其更适用于这种高速并行流水线ADC。由于所有的时钟信号均由片上的时钟振荡器产生,因此它需要一个独立的全速时钟信号。 Typically, high-resolution ADCs are based on successive approximation or oversampling architectures, but both of these architectures can not attain high speed of conversion. The pipelined analog-to-digital converter /(ADC/) is a popular structure for high-speed and high-resolution data conversion and can attain compact area and efficient power dissipation. Applications such as high-end video signal processing, high performance digital communications, and medical imaging require ADCs with sample rates approaching 100 MS//s and a dynamic range at the Nyquist bandwidth close to 60 dB. In response to these needs, there is a continued search for architectures and circuit techniques enabling a monolithic ADC to meet these specifications with a reasonable chip area and power dissipation. It is of particular interest that if such an ADC is fabricated in a standard CMOS technology. This work addresses some of the known problems inherent in time-interleaved, or parallel, pipeline ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at the maximum sampling rate up to 95 MHz in 1μm CMOS technology. It attains 59.5 dB SNDR at a low conversion rate, and more than 50 dB SNDR at 50MHz input frequency with a 95 MHz conversion rate. By using a minor offset control to suppress the fs//2 tone, 65 dB spurious free dynamic range /(SFDR/) is achieved. The ADC implemented in fully differential circuitry uses the 2-channel 3-stage pipeline architecture. Each stage converts 4-bits, and 2-bits from 12-bit are used for digital error correction. The comparator schematic are deeply identified and analyzed for the sub-ADC in the parallel pipeline architecture. A optimized comparator is presented to release the requirement of high-speed and high-resolution parallel pipeline ADCs. Because all the digital clock signals are generated from the on-chip clock buffer, it requires a single full speed clock signal.

关 键 词： 模数转换器 流水线 奈氏带宽 工艺 比较器

领　　域： [电子电信]