导　　师： 李振坤

学科专业： 081203

授予学位： 硕士

作　　者： ;

机构地区： 广东工业大学

摘　　要： 本文主要完成了基于WISHBONE总线可扩展FPGA片上系统的设计,该系统可以根据需求方便灵活地进行系统扩展。设计采用硬件描述语言Verilog进行描述,并在Xilinx公司的FPGA芯片上通过验证。 论文首先简单介绍了片上系统的发展过程,并分析了FPGA片上系统设计现存的主要问题,特别是片上总线问题和可复用设计问题。 论文首先分析了单片机应用系统的可扩展问题,并提出了基于FPGA的解决方案。然后简单介绍了无线传感器节点,并采用WISHBONE片上总线架构设计了一种基于FPGA的易扩展的无线传感器片上系统,该系统由一个8位的MCU IP核和多个外设控制器IP核组成,系统支持扩展多达16个不同接口类型的外部设备。 片上总线,是连接IP核构造成SoC的关键,同时也是可复用IP核的基础。本文介绍了目前常用的片上总线,并着重分析了WISHBONE总线,WISHBONE总线是一种简单、灵活的片上总线,非常适用于普通片上系统的开发。其只规范了IP核的接口标准,对IP核内部没有任何要求,接口实现占用资源少,并且可以自定义仲裁。可支持多种互连方式,包括有点对点、数据流、共享总线和交叉开关。 IP核复用是片上系统设计的前提,本论文按照规范的设计规则和设计流程设计了常用的数字处理IP核,包括与PIC16C5X指令相兼容的8位MCU、GPIO-WISHBONE接口、ⅡC-WISHBONE接口、ISP-WISHBONE接口和URAT-WISHBONE接口。 本论文所设计的8位MCU IP核实现了美国Microchip公司的PIC16C5X系列的33条指令集。通过对指令的分析,设计了一种基于FPGA的体系结构。在同一的模块实现和解决了系统中时钟和复位信号的同步问题;同时着重分析了跳转指令的实现和片内存储器的实现,跳转指令特别是条件跳转指令首先要进行条件判断,根据判断情况作出不同的操作选择;片内存器充分利用了XILINX ISE开发工具所提供 This paper introduces the design of extensible FPGA SoC based on WISHBONE, which function is easy to be extended.The design is described by Verilog VHL,and also implemented in the Xilinx FPGA chip. On this paper, it first introduces the development of System-on-a-Chip, and also analyses the problems of designing SoC based on FPGA,especially, On-Chip Bus and IP core reuse. It first analyses the extensible problem of SCM application system,and submits a solution based on FPGA.And then it introduces the wireless sensor node and design a extensible SoC based on FPGA,which is under WISHBONE standard.This SoC system makes up of a 8-bit MCU and some peripheral equipment controller IP core.This system can be expand to 16 slaves. Bus-On-a-Chip is the key of interconnecting different IP cores to SoC,also is the foundation of re-use IP core.This paper introduces some common Buses-On-a Chip, especially WISHBONE bus which is a simple, flexible and portalbe system bus.It defines the standard data exchange between IP core modules. It does not attempt to regulate the application specific functions of the IP core.It require few logics and the arbitration methodology is defined by the end user.Variable core interconnection methods support point-to-point, shared bus, crossbarswitch, and switched fabric interconnections. IP core reuse technology is the foundation of designing of SoC.All IP cores in the paper are designed by standard rule and flow,including 8-bit MCU compatible with PIC16C5x,GPIO controller, IIC controller, SPI controller,and UART controller. On this paper,it introduces the design of 8-bit MCU ip core which instruction is compatible with PIC16C5x.After analyzing the instruction and frame,it implement the synchronization between clock and reset signals in the same module.It completes jumping instruction, especially the condition jumping instruction by judging the condition to decide the operation.It instrduces the design of RAM module by Xilinx ISE develop tool,which is support the block RAM o

关 键 词： 可扩展 片上系统 总线 核复用

领　　域： [电子电信]