导　　师： 陈吉华

学科专业： H09

授予学位： 硕士

作　　者： ;

机构地区： 国防科学技术大学

摘　　要： 集成电路技术的快速发展为系统芯片(SYSTEM-ON-A-CHIP，SOC)的发展带来了良好的条件和契机。然而，随着芯片集成度的快速提高，SOC的设计规模和设计复杂性不断增大，而相对应的设计能力却发展缓慢，导致设计与制造技术之间的鸿沟越来越大，这使得SOC的设计者们面临着严重的困难和挑战。为了解决这种困境，我们需要将高层次的软硬件协同设计技术和基于平台的设计重用技术结合起来，构建高层次的SOC软硬件协同设计平台。 近几年提出的基于层次化平台的SOC设计方法学，将整个SOC的高层设计过程分为系统级、事务级、RTL级三个抽象层次的设计平台。在层次平台上，应用软件设计和体系结构设计可以并行进行，软硬件模块之间可以尽早的进行协同仿真和模拟，通过逐层细化、映射、仿真和约束传播进行软硬件协同设计，并且在设计时支持对以往的模块和体系结构模板进行大幅度的设计重用，从而降低了大范围设计空间探索所带来的时空消耗，提高了系统的开发速度和质量。 本文较深入的研究了层次设计平台中比较复杂的事务层SOC模板建模方法，完成的主要工作和取得的主要研究成果包括： 1)提出了一种SOC事务级模板的建模方法CCST(COMPUTATIONCOMMUNICATIONSCHEDULINGTEMPLATE)建模过程，该过程通过将事务级SOC系统中的计算、拓扑、总线协议、仲裁机制、作业调度等组成要素按照功能、通讯和调度要素分类抽象出来，然后分别进行事务级设计和验证，再通过正交耦合的方式组合起来构成整个系统，从而简化了SOC事务级系统的设计，加快了平台的设计空间探索。 2)提出了一种基于虚拟中间接口VMS(VIRTUALMIDDLESOCKET)的事务级模板仿真方法，该方法以简化软硬件模块细化过程和提高协同仿真速度为目的，通过接口通讯、数据转换和周期扫描的协同工作高效率的完成了事务级系统的功能验证和性能估算过程，为事务级的软硬件划分和功能映射提供了必要的反馈信息。 3)构造了SOC事务级平台的部分构建和仿真工具集，该工具集支持模块级、体系结构模板级以及平台级等多层次的模型设计，通过模块视图的选取和参数配置来进行平台的设计空间探索，并实现了四种事务级仿真模型，从多个角度为设计者的决策提供参考。该平台的实现有效的支持了SOC系统的事务级设计，并验证了上述建模和仿真模型。 4)分析了基于HUFFMAN编码的静态图像编码过程，在事务级SOC平台框架中构建了其中最为重要的前向离散余弦变换、矩阵量化、霍夫曼编码等几个计算模块，完成了体系结构模板的设计和平台的例化过程，最后通过设计空间探索完成了整个系统的设计。经过仿真测试，验证了该算法的功能和仿真平台工具集的有效性，进一步验证了本文提出的建模和仿真模型。 The high speed development of Integrated circuit technique brings an opportunity for the development of System-On-a-Chip /(SoC/). However, with the fast exaltation of chip integration, SoC's design scale and design complexity enlarged continuously, but the corresponding design capability evolved very slow, which makes SoC designer face a serious difficulty and challenge because of the contradiction of design and manufacture. For solving this kind of predicament, we need to put the hardware//software co-design technique in high level and Platform-Based reuse technology together to set up a new hardware//software co-design platform of SoC in high level. A Hierarchical Platform-Based Design /(Hi-PBD/) method for SoC hardware//software co-design was present in the last few years. This method divides the high level design flow of SoC system into three levels /(i.e. System Modeling Level, Transaction Level and Register Transfer Level/). On the hierarchical platform, software design and architecture design can proceed in parallel, hardware//software co-simulation can be executed as early as possible, hardware//software co-design can be handled through refining, mapping, simulation and constraint propagations, the high reuse of former module and architecture template can be support in the platform to lower the time-space consumption and improve design speed and design quality. In this paper, we deeper researched the more complicated Transaction Level Template Modeling method of Hierarchical Platform-Based Design. The main work and achievements are as follows: 1/) We advanced a Template modeling method based on CCST /(Computation Communication Scheduling Template/) process in SoC Transaction Level. In the process, computing module, topology, bus protocol, arbitration mechanism, job scheduling of SoC system are abstracted and classified by function, communicated and scheduled in transaction level. These factors would be designed and verified respectively, and then be crossly coupled to constitute the whole system, thus simplified the design of SoC system in Transaction Level, accelerated the exploration in platform's design space. 2/) We advanced a Template simulation method based on VMS /(Virtual Middle Socket/) in SoC Transaction Level. With the purpose of simplifying hardware//software refining process and accelerating hardware//software co-simulation, the method uses collaborative work of socket communication unit, data convert unit and cycle scanning unit to complete the function verify process and performance estimation process in transaction level, then provide the feedback information for hardware//software dividing and function mapping.

关 键 词： 系统芯片 层次平台 事务级建模 事务级仿真 模型 图像编码

分 类 号： [TP391.9]

领　　域： [自动化与计算机技术] [自动化与计算机技术]