机构地区: 华南师范大学
出 处: 《华南师范大学学报(自然科学版)》 2002年第1期9-12,共4页
摘 要: 本设计借助EDA设计软件“ispEXPERTVer7.0forLattice” ,使用VHDL语言 。 The design of time slot exchange controller based on a complex programmable logic device(CPLD) and with EDA and VHDL software is described. A micro-time slot exchange controller is realised by using a piece of CPLD circuit.