作　　者： ; ; ;

机构地区： 广东工业大学材料与能源学院

出　　处： 《微电子学》 2011年第1期150-154,共5页

摘　　要： 当对a-Si∶H TFT施加较大的漏-栅电压时,其泄漏电流主要取决于空穴在漏端耗尽区内的产生过程以及被有源层内中立陷阱捕获的过程。基于价带空穴和被陷阱所捕获空穴的一维连续性方程,推导出空穴在有源层内纵向传导的逃逸率。通过描述漏端耗尽区内空穴的产生率以及在a-Si∶H层内空穴传导的逃逸率,建立了a-Si∶H TFT的泄漏电流模型,并进行了相应验证。 Hole generation in drain depletion region and its subsequent trapping in bulk a-Si∶H layer are the two most important processes influencing leakage current at high drain-gate voltages in a-Si∶H TFT.Based on 1-D continuity equations for tunneling generated holes and trapped holes,a rate used to describe the escaping probability of holes in bulk a-Si∶H layer was proposed.By considering the hole generation rate in drain depletion region and the hole escaping rate in bulk a-Si∶H layer due to hole conduction,a leakage current model for a-Si∶H TFT was developed and verified using experimental data.

关 键 词： 非晶硅薄膜晶体管 泄漏电流 空穴传导 逃逸率

领　　域： [电子电信]