机构地区: 深圳信息职业技术学院
出 处: 《通信技术》 2010年第4期7-10,共4页
摘 要: 文中给出了各种最小和算法相关的LDPC码解码算法和它们的并行实现中校验节点更新的典型硬件结构。对于归一化MS的一个校验节点更新,如果当前行的权重是dc,则需要dc次乘,因此,如果dc很大,必然导致高的复杂度。提出一种新的校验节点更新方法,对于高速率LDPC码的归一化MS算法和匹配行重量的MS算法,能够明显减少比较/选择运算次数。仿真表明,Nor-MS算法和Rwm-MS算法的性能与Log-BP算法性能很相近,但复杂度大大降低。可见,Nor-MS算法和Rwm-MS算法也是LDPC码解码的一种很好的可选方法。 This paper presents various Min-Sum-related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation.For one check node update of Normalized Min-Sum algorithm(Nor-MS),if the current row weight is d c,d cmultiplications are needed.If d cis large,this would lead to high complexity.An innovative method for check node update is proposed,which could obviously reduce the number of multiplication operations for the Nor-MS algorithm and the number of comparison/selection operations for the Rwm-MS algorithm of high rate LDPC codes.Simulations indicate that the performance of Nor-MS and Rwm-MS is almost the same as that of Log-BP,namely the optimal algorithm,and that Nor-MS and Rwm-MS are good choices for LDPC decoding.