作　　者： ; ; ;

机构地区： 茂名学院计算机与电子信息学院

出　　处： 《计算机应用与软件》 2008年第11期51-52,55,共3页

摘　　要： 为解决高速CPU与低速主存储器两者速度的平衡和匹配问题,提出一种并行高速读取的存储器模型,对其结构组成、基本原理、数据读取算法以及时间估算作了分析,最后通过仿真实验验证了其正确性和可行性。该模型具备一般的猝发式存储器和双端口存储器的数据读取特点,可以高速读取成组连续数据,大幅度地提高了微处理器系统的整体性能。 A model of high-speed parallel accessing memory was brought forward to solve the problem of speed balance and match between high-speed CPU and low-speed main memory. Its structure, basic principle, data-accessing algorithm and time estimating were analyzed, and its validity and feasibility were proved through the simulating experiment. Combining the advantages of general bursting memory and dual-port memory in data accessing, this model accessed group sequential data in high speed and improved significantly the integral performance of micro processing system.

关 键 词： 存储器 端口 猝发式 地址 并行

领　　域： [自动化与计算机技术] [自动化与计算机技术] [自动化与计算机技术] [自动化与计算机技术]