作　　者： ; ; ; (陈炎）;

机构地区： 中国科学院电子学研究所

出　　处： 《测试技术学报》 2006年第3期257-263,共7页

摘　　要： 综合孔径雷达(SAR)实时成像处理器,在满足分辨率的情况下,通过预滤波和降采样的方式降低数据率来满足系统处理带宽的要求.距离向预滤波器由于其在整个信号处理机中的特殊位置决定了其需要极高的运算速度和良好的频响性能.本文对其工作原理和实现方法作了介绍,重点比较了采用TS101 DSP和XC 4V SX 35现场可编程门阵列(FPGA)实现该高性能滤波器的异同,并得出采用FPGA比采用DSP具有无法比拟优势的结论,本设计工程验证的结果说明了设计的合理性. Under the condition of meeting resolution, the SAR real-time imager can satisfy the demands of the processing band by pre-filter and down-sample. Due to being in a special position in the signal processor, the ranger pre-filter needs very high operating speed and quick frequency response. The pre-filter principles and the methods are introduced in this paper and the study is focused on the difference between TS101 DSP and XC4VSX35 FPGA in implementing high performance filter. The analysis results show that the filter with FPGA has the advantage far over the filter with DSP. In the end, the results of practical experiments are given to illuminate the design rationality.

关 键 词： 预滤波

领　　域： [电子电信] [电子电信]