作　　者： ; ; ;

机构地区： 华南理工大学电子与信息学院

出　　处： 《华南理工大学学报（自然科学版）》 2004年第11期66-69,共4页

摘　　要： 为了减少RS译码器所占用的现场可编程门阵列 (FPGA)资源 ,研究了RS码的译码算法 .提出了使用Actel公司的ProASICPLUS系列芯片实现IP包差错控制系统中RS码的译码方案 ,采用码型RS(10 0 ,81)进行纠错 .同时结合大运算量环节 ,描述了利用改进的BM算法实现译码功能的具体方案 ,该方案相对于传统的方案更能节约资源 .实验表明 ,该译码器完成了IP包差错控制的要求 ,译码器输入码流速率可达 30Mbit/s .最后介绍了ProASICPLUS系列芯片的基本结构特点及用FPGA实现的关键技术 . To reduce the FPGA resources that RS decoder occupies, the algorithm of RS decoding was studied. An approach to implement RS decoding in IP block error correction system on Actel ProASIC PLUS chip was also presented. In this approach, RS(100,81) was adopted for error correction. Based on the complicated operation, the solution to the decoder, that is, the modified BM algorithm, was then described, which can save more resources than the traditional one. Experimental results indicate that the decoder can accomplish the task of IP block error correction and can accept an input data rate up to 30Mbit/s. The primary architecture of ProASIC PLUS chip and the key technology of its implementation on FPGA were finally presented.

关 键 词： 包 码 译码器 改进的 算法 现场可编程门阵列

领　　域： [电子电信] [电子电信]