机构地区: 暨南大学理工学院电子工程系
出 处: 《微电子学与计算机》 2004年第7期150-152,共3页
摘 要: 本文提出了在ASIC中实现高速滤波器的一种新型结构,这种结构是使用流水线技术,通过对高速乘法器的合理分割并组合Wallace加法树阵列构成,采用这种结构可以实现任何阶数的高速FIR滤波器。文章最后对所设计的滤波器的各个部分进行了时延分析,并与传统结构实现的滤波器进行了性能比较。 This paper gives a description of a new certain structure that realizes the function of high-speed filter in ASIC. This structure is made into effect by a rational division of the high-speed multiplier and reorganization in Wallace adder array tree with the aide of pipelining technology. Using this structure, we can implement FIR filters with any orders. The final section of this paper will be focused on the time-lapse of every part of this designed filter and its comparison to the filter of conventional structure.
领 域: [自动化与计算机技术] [自动化与计算机技术]